1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a formation method of a barrier layer in a semiconductor device having the damascene structure.
2. Description of the Prior Art
When a metal containing copper is used for both of an upper wiring and a lower wiring, it is necessary to design the manufacturing processes by paying a special attention to electromigration (referred to as EM hereinafter) in the vicinity of a via hole connecting these wirings. What is called EM is a phenomenon in which metal atoms constituting a conductor wiring are transported in the direction of flow of the electrons by the current, and the time from application of stresses of a dc current and temperature to the conductor wiring till the disconnection of the conductor wiring is called EM life.
Wiring connection structures in a via hole include the following examples.
A first conventional structure is one in which a via plug 111 and a lower wiring 105 are connected with a barrier film 110 that prevents the diffusion of copper (Cu) atoms interposed between them, as shown in a sectional view of the vicinity of the via hole in FIG. 3A.
A second conventional structure is one in which a via plug 211 and a lower wiring 205 are connected without having a barrier film that prevents the diffusion of Cu atoms between them, as in FIG. 3B that shows Japanese Patent Applications Laid Open, No. Hei-9-312291 (a method in which no barrier film is formed between an upper and a lower wirings is also shown in Japanese Patent Applications Laid Open, No. Hei-10-261715).
The manufacturing methods of the second conventional structure in the above include the following method shown in FIG. 4. Namely, after embedding the lower wiring 205 in a first layer insulating film 203, a nitride film 206, a second layer insulating film 207, a nitride film 216 and a third layer insulating film 214 are deposited on the entire surface, a via hole 208 is formed by drilling these films in a single stroke and a trench for an upper wiring is formed by selectively removing the third layer insulating film 214 (FIG. 4A)
A barrier film 210 is deposited on the entire surface, then the barrier film 210 is etched back to leave the barrier film on the side face of the via hole 208, and Cu is deposited on top of it (FIG. 4B)
In the via hole 208, the barrier film 210 is formed only on the side face of the via hole 208, and the nitride film 206 is not formed on the top face of the lower wiring 205 and the bottom face of the via plug 211. Therefore, when viewed through the upper and lower wirings, the interfaces making contact with Cu have different structures in two regions, namely, at the interface of Cu with the barrier film 210 on the side face and at the interface with the lower wiring, in the vicinity of the via hole.
The wiring structures in the vicinity of the via hole and the methods of wiring formation described in the above have the following problems.
First, in the first conventional structure, voids are generated in the wirings at the bottom part of the via hole which gives rise to a deterioration in the EM life.
This tendency to generate defects (voids) by EM is caused when a current, namely, a flow of the electrons, is generated between the lower wiring 105 and the upper wiring 121, by the blocking of the flow of the Cu atoms accompanying the movement of the electrons. Moreover, replenishment of the Cu atoms for compensating the Cu atoms responsible for the formation of the voids is made unavailable, causing a deterioration in the EM life.
Next, in the second conventional structure, hindrance to the EM is relaxed compared with the case in the first conventional structure, nonetheless the generation of the voids occurs in the vicinity of the via hole and a deterioration in the EM life takes place. This deterioration in the EM life is due to the deterioration of the adhesion at the interface of the barrier film on the side face of the via hole and Cu embedded in the via hole, which is caused by the contamination of the surface of the barrier film during the etch-back of the barrier film.
Moreover, since no barrier film is formed between the top face of the lower wiring and the bottom face of the via hole, formation of the voids on the depletion side of Cu atoms is suppressed and the drawback in the first conventional structure is overcome. However, since the current flow concentrates at the corners where the direction of the current flow is changed by 90 and the movement of the atoms is promoted than in the surroundings, the Cu atoms flow out from there without restriction. This leads to an easy generation of the voids, which in turn results in a deterioration in the EM life. Furthermore, the materials making contact with Cu are different on the side face and on the bottom face of the upper wiring, and a discontinuity in the flow of atoms arises and the voids tend to be formed easily at the regions where the two kinds of interface (having different diffusion rates) are brought into contact.
In the manufacturing method of the second conventional structure, the barrier film is etched back and Cu atoms are deposited on the surface of the etched-back barrier film. In this method, a surface modified layer 215 indicated by the crosses due to oxidation or etch-back is formed on the interface of Cu and the barrier film, and the adhesion of the barrier film to Cu is deteriorated. The interface of the barrier film and Cu being the principal diffusion path of Cu atoms by EM, the deterioration in the adhesion of the interface leads to an increase in the diffusion rate of the Cu atoms and to a deterioration in the EM life.
Object of the Invention
It is the object of the present invention to provide a formation method of a barrier film which can excellently cope with the hindrance to the EM in connecting an upper and a lower wirings formed of a Cu containing metal in a via hole having a large aspect ratio.
The manufacturing method of a semiconductor device according to the present invention includes a step of forming a lower wiring on a semiconductor substrate, a step of forming a layer insulating film on the lower wiring, a step of forming an opening which exposes the lower wiring by removing apart of the layer insulating film, a step of forming a barrier film in the opening and a step of forming an upper wiring in the opening. The lower and upper wirings are copper containing wirings formed of copper or a copper alloy, the barrier film covers the bottom face and the side face of the opening, and the barrier film on the bottom face of the opening is formed to have a thickness which is less than twice the diffusion length of the copper atoms in the barrier film.